A power gating (PG) technology has been proposed as a technology to reduce the power consumption of integrated circuits such as complementary metal oxide semiconductor (CMOS) integrated circuits and the like. One of the challenges in the power gating technology is retaining information at the time of power shut-down. To retain information at the time of power shut-down, using a non-volatile circuit such as a non-volatile memory for a memory circuit has been studied (Patent Document 1). A low-voltage driving technique has been also studied to reduce the power consumption of the integrated circuit.